Motorola MPC8260 Instrukcja Użytkownika Pobierz pdf

This document describes implementation of the MPC8260A—the HiP4-process technology

version of the MPC8260 PowerQUICC II microprocessor—and differences between the

MPC8260A the MPC8260 (HiP3 version). All of the information in the

MPC8260

PowerQUICC II User’s Manual

(which applies to the HiP3 process) also applies to the

MPC8260A with the exceptions and additions noted in this document. In the event

information in the two documents conﬂict, information presented here supersedes that in the

MPC8260 PowerQUICC II User’s Manual

NOTE

Section, table, and ﬁgure numbering in this document

indicates the chapter in the

MPC8260 PowerQUICC II

User’s Manual

to which each item corresponds. HiP4

additions and changes do not pertain to all chapters;

therefore, not all chapters are referred to in this document.

A revision history of this document is provided at the end.

MPC826

A Devices and Documentation

Motorola offers four HiP4-enhanced derivatives

of the MPC8260 PowerQUICC II family.

Table 1 shows the functionality that deﬁnes each derivative.

Until the current

MPC8260 PowerQUICC II User’s Manual

(Rev 0) is updated, several

addendum documents like this one supply information about the functionality of

HiP4-enhanced PowerQUICC II devices. Table 2 lists each device and its related

documentation.

Table 1. HiP4 MPC826

A PowerQUICC II Family Derivatives

Functionality

Derivatives

MPC8260A MPC8264A MPC8265A MPC8266A

HiP4 Process Enhancements

XXXX

PCI Bridge

Transmission Convergence (TC) Layer

Inverse Multiplexing for ATM (IMA)

Addendum

MPC8260AUMAD/D

Rev. 0.1, 2/2002

MPC8260 PowerQUICC II™

User’s Manual:

MPC8260A (HiP4)

Supplement

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

1 2 3 4 5 6 ... 19 20

Podsumowanie treści

Strona 1 - Addendum

This document describes implementation of the MPC8260A—the HiP4-process technologyversion of the MPC8260 PowerQUICC II microprocessor—and differences

Strona 2 - Overview (Chapter 1)

10 MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement MOTOROLASystem Interface Unit (SIU) (Chapter 4)MPC826xA Architecture Overview

Strona 3 - Memory Map (Chapter 3)

MOTOROLA MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement 11System Interface Unit (SIU) (Chapter 4)MPC826xA Architecture OverviewTab

Strona 4

12 MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement MOTOROLASystem Interface Unit (SIU) (Chapter 4)MPC826xA Architecture Overview

Strona 5 - 4.2.1 Interrupt Conﬁguration

MOTOROLA MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement 13MPC8260A Reset (Chapter 5)Transfer Code Signals TC[0–2]MPC8260A Reset (C

Strona 6

14 MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement MOTOROLACommunications Processor Module Overview (Chapter 13)MPC8260A RISC Cont

Strona 7 - 4.2.1.2 (New) INT Interrupt

MOTOROLA MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement 15Communications Processor Module Overview (Chapter 13)MPC8260A RISC Contr

Strona 8

16 MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement MOTOROLACommunications Processor Module Overview (Chapter 13)MPC8260A CP Comman

Strona 9 - Registers

MOTOROLA MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement 17Parallel I/O Ports (Chapter 35)MPC8260A Dual-Port RAM13.5 MPC8260A Dual-

Strona 10 - Register 1 (TESCR1)

18 MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement MOTOROLAParallel I/O Ports (Chapter 35)MPC8260A Port A Modiﬁcations 35.5.1 MPC

Strona 11 - 16 17 18 19 20 21 22 23 24 31

MOTOROLA MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement 19Parallel I/O Ports (Chapter 35)Document Revision HistoryDocument Revisio

Strona 12 - 16 17 18 19 20 21 31

2 MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement MOTOROLA Overview (Chapter 1)Features Overview (Chapter 1) This section summa

Strona 13 - 60x Bus (Chapter 8)

MPC8260AUMAD/DHOW TO REACH US:USA/EUROPE/LOCATIONS NOT LISTED:Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 o

Strona 14 - (Chapter 13)

MOTOROLA MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement 3 Memory Map (Chapter 3)MPC826xA Architecture OverviewFigure 1-1 MPC826x

Strona 15

4 MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement MOTOROLA Memory Map (Chapter 3)MPC826xA Architecture Overview Interrupt Contr

Strona 16 - 13.4.1.1 MPC8260A CP Commands

MOTOROLA MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement 5 System Interface Unit (SIU) (Chapter 4)MPC826xA Architecture Overview

Strona 17 - 13.5 MPC8260A Dual-Port RAM

6 MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement MOTOROLA System Interface Unit (SIU) (Chapter 4)MPC826xA Architecture Overview

Strona 18

MOTOROLA MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement 7 System Interface Unit (SIU) (Chapter 4)MPC826xA Architecture Overview

Strona 19 - Document Revision History

8 MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement MOTOROLA System Interface Unit (SIU) (Chapter 4)MPC826xA Architecture Overview

Strona 20

MOTOROLA MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement 9System Interface Unit (SIU) (Chapter 4)MPC826xA Architecture Overview4.3.

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