Motorola MPC8260 Instrukcja Użytkownika Pobierz pdf (Strona 5)

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MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement

System Interface Unit (SIU) (Chapter 4)MPC826xA Architecture Overview

System Interface Unit (SIU) (Chapter 4)

The MPC8260A SIU is the same as the HiP3 version with the exception of ﬁelds that have been added to

the bus transfer error status and control registers (TESCR1 and L_TESCR1). These additions are described

in the following sections.

The interrupt priorities of the PCI bridge (MPC8265A and MPC8266A only) and TC layer (MPC8264A

and MPC8266A only) are also programmed in the SIU. For descriptions of the additional register ﬁelds

related to the PCI bridge and the TC layer, refer to the

PCI Bridge Functional Speciﬁcation

and the

TC Layer

Functional Speciﬁcation

(see Table 2

4.2.1 Interrupt Conﬁguration

In Figure 4-8, note the MPC8260A’s additional sources for machine check interrupts. Also note that in

addition to the internal sources, external pins, and CPM, the interrupt controller receives interrupts from the

PCI bridge (MPC8265A and MPC8266A only) and TC layer (MPC8264A and MPC8266A only).

SI1 Registers

Same

MCC1 Registers

Same

SI2 Registers

Same

MCC2 Registers

Same

RAM

Same

Table 3-1. Additions to the Internal Memory Map (Continued)

Internal Address Abbreviation Name Size Section/Page Number

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1 2 3 4 5 6 7 8 9 10 ... 19 20

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Motorola MPC8260 Instrukcja Użytkownika Strona 5