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MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement

Memory Map (Chapter 3)MPC826xA Architecture Overview

Figure 1-1 MPC826xA Block Diagram

Memory Map (Chapter 3)

Table 3-1 shows the HiP4 additions to the internal memory map of the MPC8260A. Note that PCI and TC

layer portions of the memory map can be found in separate documentation (see Table 2).

Table 3-1. Additions to the Internal Memory Map

Internal Address Abbreviation Name Size Section/Page Number

CPM Dual-Port RAM

04000–05FFF DPRAM Dual-port RAM (microcode only) 8 Kbytes —

06000–07FFF Reserved — 8 Kbytes —

General SIU

Same as

MPC8260 Power QUICC II User’s Manual

Memory Controller

Same for MPC8260A. For PCI registers, refer to the

PCI Bridge Functional Speciﬁcation

(see Table 2).

System Integration Timers

Same

16 Kbytes

G2 Core

I-Cache

I-MMU

16 Kbytes

D-Cache

D-MMU

Communication Processor Module (CPM)

Timers

Parallel I/O

Baud Rate

Generators

32 Kbytes

32-bit RISC Microcontroller

and Program ROM

Serial

DMAs

4 Virtual

IDMAs

60x-to-PCI

Bridge

2,3

Bridge

Memory Controller

Clock Counter

System Functions

System Interface Unit

(SIU)

Local Bus

32 bits, up to 83 MHz

PCI Bus

2,3

32 bits, up to 66 MHz

MCC1 MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI

Serial Interface

3 MII 2 UTOPIA

PortsPorts

60x Bus

1. MPC8264A

2. MPC8265A

3. MPC8266A

Notes

Microcode

IMA

1,3

Dual-Port RAM

Interrupt

Controller

Time Slot Assigner

TC Layer Hardware

1,3

8 TDM Ports

Non-Multiplexed

I/O

60x-to-Local

Bus Interface Unit

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