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MPC8260 PowerQUICC II™ User’s Manual: MPC8260A (HiP4) Supplement

System Interface Unit (SIU) (Chapter 4)MPC826xA Architecture Overview

• Memory controller for parity/ECC errors. See Section 10.2.6, “Machine Check Interrupt (MCP)

Generation.”

• PCI bridge (MPC8265A and MPC8266A only)

• Bus monitor time out on an address only transaction. See Section 4.1.1, “Bus Monitor.”

When the internal core is enabled, the MCP sources listed cause the interrupt controller to send a machine

check interrupt to the core. When the core is disabled, the MCP assertion is reﬂected on IRQ0

/NMI_OUT

so an external core can serve it.

4.2.1.2 (New) INT Interrupt

Besides the MCP sources, all other interrupts are taken by the core through the INT interrupt. If the internal

core is disabled, INT is reﬂected on IRQ7

/INT_OUT so an external core can serve it.

The interrupt controller allows masking of each interrupt source. Multiple events within a CPM sub-block

event are also maskable.

4.2.2 MPC8260A Interrupt Source Priorities

Table 4-3 shows prioritization of all the MPC8260A interrupt sources. The PCI bridge interrupt source is

included in the XSIU locations and is discussed in

PCI Bridge Functional Speciﬁcation

; the TC layer

interrupt priority is conﬁgured with the SCCs in the YCC entries and is discussed in

TC Layer Functional

Speciﬁcation

(see Table 2

See Table 4-2 of the

MPC8260 User’s Manual

for more information on interrupt

source priority levels.

4.2.4 MPC8260A Interrupt Vector Encoding

Table 4-3 lists the MPC8260A encodings (including the PCI bridge [MPC8265A and MPC8266A only] and

the TC layer [MPC8264A and MPC8266A only]) for the six low-order bits of the interrupt vector.

Table 4-3. Encoding the Interrupt Vector

Interrupt Number Interrupt Source Description Interrupt Vector

0 Error (No interrupt) 0b00_0000

1 I

C 0b00_0001

2 SPI 0b00_0010

3 RISC Timers 0b00_0011

4 SMC1 0b00_0100

5 SMC2 0b00_0101

6 IDMA1 0b00_0110

7 IDMA2 0b00_0111

8 IDMA3 0b00_1000

9 IDMA4 0b00_1001

10 SDMA 0b00_1010

11 Reserved 0b00_1011

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1 2 3 4 5 6 7 8 9 10 11 12 ... 19 20

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