Motorola DSP56800 Podręcznik Użytkownika Pobierz pdf (Strona 162)

100

101

Inline Assembly Language and Intrinsics

Intrinsic Functions

162

Targeting MC56F83xx/DSP5685x Controllers

L_msu

Multiply two 16-bit fractional values and subtract this product from a 32-bit fractional

value, saturating if necessary. Generates a 32-bit result.

Assumptions

OMR’s SA bit was set to 1 at least 3 cycles before this code, that is, saturation on data

ALU results enabled.

Prototype

Word32 L_msu(Word32 laccum, Word16 sinp1, Word16 sinp2)

Example

short s1 = 0xC000;/* - 0.5 */

short s2 = 0xC000;/* - 0.5 */

long result, Acc = 0;

result = L_msu(Acc,s1,s2);

// Expected value of result: 0.25

L_mult

Multiply two 16-bit fractional values generating a signed 32-bit fractional result.

Saturates only for the case of 0x8000 x 0x8000.

Assumptions

OMR’s SA bit was set to 1 at least 3 cycles before this code, that is, saturation on data

ALU results enabled.

Prototype

Word32 L_mult(Word16 sinp1, Word16 sinp2)

1 2 ... 157 158 159 160 161 162 163 164 165 166 167 ... 445 446

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