Motorola MPC5200 Instrukcja Użytkownika Pobierz pdf (Strona 12)

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This bus is used internally to access both the NOR Flash and the NAND Flash. The NOR

Flash uses bits 31 to 24 for data and bits 23 to 0 for address. The NAND Flash uses bits

31 to 24 for its multiplexed address/data interface. Bit 3 functions as the Command Latch

Enable and bit 2 functions as the Address Latch Enable. The FLASH_CE_L bit must be

active (low) to access the NAND Flash. The RY/BY signals from the Flash devices are

not connected so software will have to query the Flash device.

When booting, the LocalPlus bus is configured as non-multiplexed, 8-bit data, 24-bit

address, maximum wait state (48 IPB_CLK cycles) and no endian swapping. The base

address for the boot device is 0xFFF0 0100. LP_CS0_L, which accesses the NOR flash,

is the only chip select immediately useable when the MPC5200 comes out of reset.

All three modes of the bus are available to the main board. Chip selects 2 through 5 are

available to the main board.

Table 4. Bus modes

MPC5200 Non-Mux-ed Mux-ed

Data

Signal Pin 24/8 16/16

Address

Tenure

32 16 8

PCI

EXT_AD[31] V1 D[7] D[15] 0 D[31] D[15] D[7] PCI_AD[31]

EXT_AD[30] R3 D[6] D[14] TSIZE[0] D[30] D[14] D[6] PCI_AD[31]

EXT_AD[29] W1 D[5] D[13] TSIZE[1] D[29] D[13] D[5] PCI_AD[29]

EXT_AD[28] T3 D[4] D[12] TSIZE[2] D[28] D[12] D[4] PCI_AD[28]

EXT_AD[27] Y1 D[3] D[11] 0 D[27] D[11] D[3] PCI_AD[27]

EXT_AD[26] T2 D[2] D[10] BS[1] D[26] D[10] D[2] PCI_AD[26]

EXT_AD[25] W2 D[1] D[9] BS[0] D[25] D[9] D[1] PCI_AD[25]

EXT_AD[24] U3 D[0] D[8] A[24] D[24] D[8] D[0] PCI_AD[24]

EXT_AD[23:16]

W3, V3,

Y3, V2, Y4,

V4, Y5,

A[23:0] D[7:0] A[23:16] D[23:16] D[7:0] 0 PCI_AD[23:16]

EXT_AD[15:8]

U8, W9,

V8, Y9, V9,

Y10, V10,

W11

A[15:8] A[15:0] A[15:8] D[15:8] 0 0 PCI_AD[15:8]

EXT_AD[7:0]

Y11, U11,

W12, V11,

Y12, V12,

W13, V13

A[7:0] A[7:0] A[7:0] D[7:0] 0 0 PCI_AD[7:0]

Note: In PCI mode, Address bit 26 is used as the MPC5200’s IDSEL

3.5 JTAG/COP

A standard JTAG interface to the MPC2500 is available. TDI is the serial data input to

the JTAG and TDO is the serial data out. The JTAG interface can also function in COP

(Common On-chip Processor) mode for extended test and debug capability. See the

MPC5200 User Manual, Section 21 for details including the COP connector pin-out. The

JTAG signals are pulled up on the p2Engine with the exception of TDO.

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 20 21

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