Motorola MF800 Instrukcja Użytkownika

PowerDAQ User Manual PowerDAQ PD2/PDXI-MF/MFS and PDL-MF DAQ boards High-Performance Multifunction I/O boards for PCI and Compact PCI/P

How to Use This Manual viii Who Should Read This Book? This manual has been designed to benefit the user of PowerDAQ boards. To use PowerDAQ, it is

Chapter 4: PowerDAQ Software (SDK) 88 • Enable and start analog output waveform generation # _PdAOutEnableConv(…) use 1 as dwEnable # _PdAOutSwS

Chapter 4: PowerDAQ Software (SDK) 89Stop acquisition • Issue a stop trigger if external trigger was not configured # _PdAOutSwStopTrig() • Di

Chapter 4: PowerDAQ Software (SDK) 90 Method C. Buffered polled-I/O waveform mode See SDK Example AoutBlock.vbp Buffered polled-I/O waveform mo

Chapter 4: PowerDAQ Software (SDK) 91 • Continue waveform generation # _PdAOutEnableConv(…) use 1 as dwEnable # _PdAOutSwStartTrig(…) • Sleep

Chapter 4: PowerDAQ Software (SDK) 92 Method D. Auto-retriggerable waveform mode (no CPU usage) See SDK Example SimpleTest.dpr Auto-regenerat

Chapter 4: PowerDAQ Software (SDK) 93 # _PdAOutEnableConv(…) use 1 as dwEnable # _PdAOutSwStartTrig(…) Stop acquisition • Reset analog output s

Chapter 4: PowerDAQ Software (SDK) 94 Digital Input/Output Subsystems The digital input/output subsystem can be used in two ways. Method A: 16-bi

Chapter 4: PowerDAQ Software (SDK) 95 Configuration word is explained in Digital I/O Architecture section of this manual. • Read status of digital

Chapter 4: PowerDAQ Software (SDK) 96 Method B. Generate event when specified edge is detected See SDK Example DIEvents.c This method is very s

Chapter 4: PowerDAQ Software (SDK) 97# _PdGetUserEvent(…) should return eDInEvent flag in the status word. • Read status of digital input latch

How to Use This Manual ix The Glossary contains an alphabetical list and description of terms used in this manual. Index The Index alphabetically li

Chapter 4: PowerDAQ Software (SDK) 98 User Counter-Timer Subsystem PD2/PDXI The User Counter-Timer subsystem can be used in many different ways. Co

Chapter 4: PowerDAQ Software (SDK) 99 Initialization • Reset UCT subsystem # _PdUctReset(…)clears latch and configuration register Set up UCT co

Chapter 4: PowerDAQ Software (SDK) 100 # _PdUctReset(…) Note To write to the counter-timer, an input clock must be applied to appropriate UCT.

Chapter 4: PowerDAQ Software (SDK) 101 PowerDAQ Example Programs A complete range of sample programs with source code is included with your PowerDA

Chapter 4: PowerDAQ Software (SDK) 102 SimpleTest application which allows Analog Input, Analog Output, Digital Input, Digital Output and Counter T

Chapter 4: PowerDAQ Software (SDK) 103 Third Party Software Support The PowerDAQ CD contains drivers for most of the popular third party software p

105 5 Calibration

Chapter 5: Calibration 106Calibration Overview This chapter contains information on the calibration procedures for the A/D and D/A subsystems on th

107 A Appendix A: Specifications

How to Use This Manual x

Appendix A: Specifications 108 PowerDAQ II Board Acquisition Timing The table below shows continuous acquisition and timing delays controlled by t

Appendix A: Specifications PDXI-MF Series Timing: ID OMEGA Model Res / Speed / Gain Fast Acq Delay Slow Acq Delay 1 PDXI-MF-1M/12L 12, 1.25

Appendix A: Specifications

111 B Appendix B: Accessories

Appendix B: Accessories 112Accessories The following accessories are available for the PowerDAQ PD2/PXI boards. Screw Terminal Panels (PDL-MF only

Appendix B: Accessories 113 BNC Connection Panels (PD2/PDXI) PD-BNC-16 16-channel BNC panel for 16-channel boards PD-BNC-16-KIT Complete Kit: Incl

Appendix B: Accessories 114Thermocouple Input Racks (All) PD-TCR-16-J 16-channel Isolated Thermocouple Input Rack—Type J PD-TCR-16-K 16-channel Iso

Appendix B: Accessories 115Cables (PD2/PDXI) PD-CBL-96 96-way pinless, 1m round, shielded cable with metal cover plates PD-CBL-96-6FT 96-way pinle

Appendix B: Accessories 116Signal Conditioning Expansion Units (All) PD-SCXU-F8 8 Anti-aliasing filters PD-SCXU-F16 16 Anti-aliasing filters PD-S

117 C Appendix C: Application Notes

1 1 Introduction

Appendix C: Application Notes 118Application Note: 1 PowerDAQ Advanced Circular Buffer (ACB) The Advanced Circular Buffer solves many of the probl

Appendix C: Application Notes 119To receive notification on a sample or scan count boundary, the buffer is segmented into frames. Whenever the data

Appendix C: Application Notes 120Circular Buffer In the Circular Buffer mode the buffer head and tail wrap to the beginning of the buffer when the

Appendix C: Application Notes 121Frame MarkersBuffer TailBuffer HeadBoard/DriverWrite New DataAt Buffer HeadApplicationReads Data FromBuffer TailDr

Appendix C: Application Notes 122Application Note: 2 PD-BNC-xx wiring options: Voltage dividers In order to build a voltage divider, resistors shou

123 D Appendix D: Warranty

Appendix D: Warranty 124Overview IBM, IBM PC/XT/AT and IBM PS/2 are trademarks of International Business Machine Corporation. BASIC is a trademark o

Appendix D: Warranty 125Omega Engineering warrants that the products furnished under this agreement will be free from material defects for a period

127 EAppendix E: Glossary

Chapter 1: Introduction 2 About the PowerDAQ board This chapter describes the basic features of the PowerDAQ boards. Overview Thank you for purchasin

Appendix E: Glossary 128Glossary A A/D Analog-to-digital. ADC Analog-to-Digital Converter. An integrated circuit that converts an analog voltage

Appendix E: Glossary 129 (2) Software - A property of a function that begins an operation and returns prior to the completion or termination of th

Appendix E: Glossary 130 amount of memory required to store one byte of data. C Cache High-speed processor memory that buffers commonly used instru

Appendix E: Glossary 131Component Software An application that contains one or more component objects that can freely interact with other component

Appendix E: Glossary 132 DAC Conversion Start signal used to start the conversion process of digital value to an analog output. The source of this

Appendix E: Glossary 133 DNL Differential Non-linearity: A measure in LSB of the worst-case deviation of code widths from their ideal value of 1 LS

Appendix E: Glossary 134 opaque areas, a light source, and a photo detector. EPROM Erasable Programmable Read-Only Memory: ROM that can be erased

Appendix E: Glossary 135 program by means of graphical screen displays. GUIs can resemble the front panels of instruments or other objects associate

Appendix E: Glossary 136 Integral Control A control action that eliminates the offset inherent in proportional control. Integrating ADC An ADC wh

Appendix E: Glossary 137 K Kilo, the prefix for 1,024, or 210, used with B in quantifying data or computer memory. kbytes/s A unit for data tran

Chapter 1: Introduction 3 PowerDAQ Models PowerDAQ model numbers are derived from the following: [Family]-[Type Of Board]-[Channels]-[Speed]/[Resolut

Appendix E: Glossary 138 N Noise An undesirable electrical signal. Noise comes from external sources such as the AC power line, motors, generators,

Appendix E: Glossary 139 Output Settling Time The amount of time required for the analog output voltage to reach its final value within specified l

Appendix E: Glossary 140 networking protocols, and special-purpose digital and analog I/O ports. Plug and Play ISA A specification prepared by Mic

Appendix E: Glossary 141through a communications channel, such as the GPIB. Q Quantization Error The inherent uncertainty in digitizing an analog

Appendix E: Glossary 142 SE Single-Ended: A term used to describe an analog input that is measured with respect to a common ground. Scan Set of

Appendix E: Glossary 143 Subroutine A set of software instructions executed by a single line of code that may have input and/or output parameters.

Appendix E: Glossary 144 Thermocouple A temperature sensor created by joining two dissimilar metals. The junction produces a small voltage as a fun

Index 145 Index _ _PdAdapterEnableInterrupt ... 77 _PdAInAsyncInit...65 _PdAInAsyncStart ... 64, 65 _PdAInAsyncStop...

Index 146 C Calibration ...95 Calibration DACs ...26 CE Mark CE Mark Certification ... 117 Channel

Index 147M Maximum per channel rate...32 Multi-board operation ... 72 Multiplexors...28 Multithreaded applications

Chapter 1: Introduction 4 PD2-MF-16-1M/12H 1.25 MS/s, 12-bit, 16SE/8DI A/D, Gains: 1,2,4,8; Two 12-bit D/A PD2-MF-64-1M/12L 1.25 MS/s, 12-bit, 64SE

Index 148 voltage divider...114 W WaitForSingleObject ...64 WaitForSingleObject ... 73 Warranty ...

Index 149

Reader EvaluationWe are committed to improving the quality of our documentation, in order to serve you better. Your feedback will help us in the eff

Chapter 1: Introduction 5 PowerDAQ PD2-MFS Series: Model: Analog features: PD2-MFS-4-2M/14 1.65 MS/s, 14-bit, 4SE Simultaneous Sample & Hold;

Chapter 1: Introduction 6 Note The PD2-MFS series have onboard sample and hold amplifiers for each channel. These are part of the boards hardware

Chapter 1: Introduction 7 PDXI-MF-16-333/16L 333 kS/s, 16-bit, 16SE/8DI A/D, Gains: 1,10,100,1000; Two 12-bit D/A PDXI-MF-16-333/16H 333 kS/s, 16-b

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form by any means, electron

Chapter 1: Introduction 8 Two 12-bit D/As PDXI-MFS-4-500/14 500 kS/s, 14-bit, 4SE Simultaneous Sample & HoldTwo 12-bit D/As PDXI-MFS-8-500/14 50

Chapter 1: Introduction 9 Upgrade Part Number: Additional features added: PD2-MFS-4-DG4 Upgrade any PD2-MFS board from 4SE to 4DI with Gains (1,2,5

PowerDAQ PDL-MF Lab Board: This low cost Lab series board features: PDL-MF 150 kS/s, 16-bit, 16SE/16PDI, 8DI ; Two 12-bit D/As, 48 DIO and 3 CTM

11 2 Installation and Configuration

Chapter 2: Installation and Configuration 12 Before You Begin Before you install your PowerDAQ board, you should read and understand the following i

Chapter 2: Installation and Configuration 13Installing PowerDAQ Installing the Board: To install your PowerDAQ board: 1. Turn off your PC and rem

Chapter 2: Installation and Configuration 14Installing the Software To install the PowerDAQ SDK: 1. Start your PC and, if you are running Windows

Chapter 2: Installation and Configuration 157. If the Setup program asks for information about third-party software packages that you do not have i

Chapter 2: Installation and Configuration 16Configuring the PowerDAQ Board J2 ConnectorJ1 Connec torInp ut Mul ti ple xorsJ4 ConnectorJ6 Connector

Chapter 2: Installation and Configuration 17J1 ConnectorPCI BusDSPPowerDAQ PDL-MF board1BootROMPowerDAQ Figure 4: PDL-MF- Board connector layout I

Table of Contents i Table of Contents How to Use This Manual... vi Introduction .

Chapter 2: Installation and Configuration 18 Figure 5: Single-ended Inputs and pseudo-differential inputs Note Unused channels should be shorte

Chapter 2: Installation and Configuration 19 Note Positive and negative differential inputs should not be driven by voltages more then AGND ±14V.

Chapter 2: Installation and Configuration 20 Note PXI boards are synchronized via PXI interface using the PXI Configurator program. Figure 7: PD

Chapter 2: Installation and Configuration 21Test Program: After you have wired an application to your PowerDAQ board, you should run the Simple Tes

Chapter 2: Installation and Configuration 22• 36-pin internal digital connector (J2) Manufactured by: Thomas and Betts PN# 609-3627 (Male) http://

Chapter 2: Installation and Configuration 23J1 Connector (Single-Ended Mode) 2150493514525536547558565710 5811 5912 6013 616215 6316 6417 6518 6619

Chapter 2: Installation and Configuration 24J1 Connector (Differential Input Mode) 2150493514525536547558565710 5811 5912 6013 616215 6316 6417 6518

Chapter 2: Installation and Configuration 25Connector Pin Assignments for J2 The J2 digital internal connector contains eight digital input and eigh

Chapter 2: Installation and Configuration 26Connector Pin Assignments for J4 The J4 Connector contains eight digital input and eight digital output

Chapter 2: Installation and Configuration 27Connector Pin Assignments for J6 The J6 Interboard Synchronization Connector contains two pairs of clock

Table of Contents ii Triggering...55 Digital Input/Output Subs

Chapter 2: Installation and Configuration 28Connector Pin Assignments for PDL-MF J1 TMR0DGNDTMR1DGNDTMR2DGNDDOUT22DOUT20DOUT18DOUT16DOUT14DOUT12DOUT

Chapter 2: Installation and Configuration 29Connector Pin Assignments for PDXI J2 DOUT11DIN13DOUT12DIN14DOUT13DIN15DOUT14DOUT15DGNDDGNDDGNDDGNDDGNDD

Chapter 2: Installation and Configuration 30PXI lines support Following PXI lines may be used for the synchronization: PXI_TR16 0..7, PXI_STAR

31 3 Architecture

Chapter 3: Architecture 32Functional Overview PowerDAQ PD2-MF/MFS series have very extensive input modes, clocking and triggering capabilities as

Chapter 3: Architecture 33+-External A nal og I/O Connec tor(64)PowerDAQ IIData Acqu isitionControl andTiming LogicDAC0DAC 1VoltageReferenceAOut

Chapter 3: Architecture 34+-Po werDA Q I IData AcquisitionControl andTimin g Log icDAC0DAC1Volt ag eReferenceAOut CalibrationDACsAnalogOut putAmpli

Chapter 3: Architecture 35input channels simultaneously and then hold the acquired voltages while the ADC converts channel by channel. • The Progr

Chapter 3: Architecture 36Digital Input/Output subsystem includes • 16-bit input register to read logical levels on digital input lines (24-bit o

Chapter 3: Architecture 37Analog Input Subsystem The analog input front-end multiplexes multiplex the first stage of the input channels (64/16 sin

Table of Contents iii Appendix E: Glossary...127 Glossary ...

Chapter 3: Architecture 38 Figure 13: PowerDAQ Multifunction Board front-end MFS boards have sample and hold amplifiers (S

Chapter 3: Architecture 39 Figure 14: PowerDAQ Sample and Hold Board front-end The major difference between MF and MFS boards are

Chapter 3: Architecture 40 Figure 15: PD2/PDXI Series Acquisition Process Figure 16: PD2/PDXI Acquisition Pro

Chapter 3: Architecture 41Figures 10 and 11 show the differences in data acquired using MF and MFS boards. When a sine wave is applied to the chan

Chapter 3: Architecture 42 Note Complete timing tables for all PowerDAQ boards are located Appendix A. Input Modes Single Ended The PowerDAQ

Chapter 3: Architecture 43 Differential Inputs Differential inputs allow up to 32 channels. (Differential inputs use two analog input channels. On

Chapter 3: Architecture 44 Input Ranges The PowerDAQ boards have four possible input ranges. These are global settings. UNIPOLAR BIPOLAR 0V to +

Chapter 3: Architecture 45 Channel List The Channel List contains sequences of channels to be acquired and their per channel gains. This sequence

Chapter 3: Architecture 46 Clocking The PowerDAQ board has two selectable base frequencies (11 MHz and 33 MHz) to clock acquisition. Lower frequen

Chapter 3: Architecture 47 Clock combination Typical use CL Clock source CV Clock source SW Continuous Acquire one set of data points (one sca

Table of Contents iv List of Figures Figure 1: Control Panel Application ...15 Figure 2: PD2- B

Chapter 3: Architecture 48 Triggering The Analog input subsystem needs a trigger signal to start and stop acquisition. The Trigger signal is selec

Chapter 3: Architecture 49 Start trigger edge Stop trigger edge External TTL signal Rising Rising Rising Falling Falling Falling Falling

Chapter 3: Architecture 50 Data format Data in the data stream has the following format. Each two consecutive bytes contain a single sample from t

Chapter 3: Architecture 51 The following calculations should be performed to convert the raw, stored hexadecimal data to scaled (Voltage) data: 1.

Chapter 3: Architecture 52 7. To convert voltage into analog output value you can use following formulas: For all other models Value = ((HexData

Chapter 3: Architecture 53 Analog Output Subsystem Analog output subsystem contains two DACs (Digital to Analog Converters) and supports the follo

Chapter 3: Architecture 54Auto-regeneration Waveform (circular waveform) Auto-regeneration waveform mode can be used to create fixed length wavef

Chapter 3: Architecture 55 The two Hex values for Aout channel 0 and 1 respectively can be combined to write to the analog output as follows: Value

Chapter 3: Architecture 56Digital Input/Output Subsystem Digital Output subsystem contains one 16-bit (PD2/PDXI-MF/MFS) and 24-bit (PDL-MF) output

Chapter 3: Architecture 57 Latch configuration is a 16-bit word, two bits for each one of eight sense inputs. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B

Table of Contents v List of Tables Table 1: PowerDAQ PD2-MF Models ...4 Table 2: PowerDAQ PD2-MFS

Chapter 3: Architecture 58 User Counter-Timer Subsystem PD2/PDXI User counter-timer is based on the Intel 82C54 16-bit counter-timer chip. It conta

Chapter 3: Architecture 59Special frequency measurement mode is implemented on PD2/PDXI boards. Using this mode external frequency may be measured

Chapter 3: Architecture 60

61 4 PowerDAQ Software Development Kit (PD-SDK)

Chapter 4: PowerDAQ Software (SDK) 62PowerDAQ Software PowerDAQ SDK Structure The installation will create the following directory structure in Pr

Chapter 4: PowerDAQ Software (SDK) 63Location: \winnt\system32\drivers Files: pwrdaq.sys device driver PowerDAQ DLLs The PowerDAQ software includ

Chapter 4: PowerDAQ Software (SDK) 64/lib pwrdaq32.lib - MSVC/MSVS v.5.x, 6.x pd32bb.lib - Borland C Builder v.3.0, 4.0 pd16bb.lib - 1

Chapter 4: PowerDAQ Software (SDK) 65/include/vb3 pwrdaq16.bas - API function prototypes and structures file for Visual Basic v.3.0 pdfw_def.bas

Chapter 4: PowerDAQ Software (SDK) 66 Communication between user application and PowerDAQ PD2/PDXI/PDLboard Figure 21: Communica

Chapter 4: PowerDAQ Software (SDK) 67Programming subsystems All PowerDAQ subsystems have two modes of operation: • Polled • Event-based Polled

How to Use This Manual vi How to Use This Manual Introduction This manual describes the hardware of each of the PowerDAQ series of PCI and PXI DAQ b

Chapter 4: PowerDAQ Software (SDK) 68Analog Input Subsystem There are many ways of working with the analog input subsystem. Before you start progr

Chapter 4: PowerDAQ Software (SDK) 69 Method A. Single scan operation See SDK Examples SimpleAin.c, simplescan.pas, simplescan.bas, vm64.pas, v

Chapter 4: PowerDAQ Software (SDK) 70 Acquisition - call the acquisition sequence using the timer or in a program loop. Allow all points in the sc

Chapter 4: PowerDAQ Software (SDK) 71 Note The PowerDAQ boards have a special “slow bit” in the channel list. You might want to increase settlin

Chapter 4: PowerDAQ Software (SDK) 72Method B. Burst Buffered Acquisition – One Shot See SDK Examples Stream2.c, SimpleExample.vbp This method i

Chapter 4: PowerDAQ Software (SDK) 73 dwCfg = (AIB_CVSTART0 | AIB_CVSTART1 | AIB_CLSTART1) for external clock Add AIB_INTCLSBASE constant to select

Chapter 4: PowerDAQ Software (SDK) 74 your buffer with samples. When it returns event from the board you have to check what caused it • Check even

Chapter 4: PowerDAQ Software (SDK) 75 # _PdUnregisterBuffer(…) # _PdFreeBuffer(…) Note External trigger. If you want your acquisition process

Chapter 4: PowerDAQ Software (SDK) 76 Trigger type Configuration Start trigger rising edge AIB_STARTTRIG0 Start trigger falling edge AIB_STARTT

Chapter 4: PowerDAQ Software (SDK) 77 Method C. Continuous Acquisition using ACB See SDK Examples Stream2.c Method C uses the PowerDAQ Advanced

How to Use This Manual vii PowerDAQ PDXI-MF Multifunction Series: PDXI-MF-16-2M/14H PDXI-MF-16-150/16L PDXI-MF-64-2M/14H PDXI-MF-16-150/16H PDXI-MF-

Chapter 4: PowerDAQ Software (SDK) 78 # WaitForSingleObject(hEventObject, Timeout) This function puts your program into a sleep mode and gives pro

Chapter 4: PowerDAQ Software (SDK) 79 data in a one piece. This eliminates need of the user application to take care about data wrap around situati

Chapter 4: PowerDAQ Software (SDK) 80 How to find optimal frame size for data acquisition? The following should be taken into account wh

Chapter 4: PowerDAQ Software (SDK) 81 Method D. Retrieving ‘always-fresh’ data using ACB recycled mode See SDK Examples Stream2.c Another very

Chapter 4: PowerDAQ Software (SDK) 82Method F. Multi-board operations. Stream to disk applications See SDK Examples stream4.c, SingleBoardStreamB

Chapter 4: PowerDAQ Software (SDK) 83 Method G. Combining Analog and Digital subsystems See SDK Examples SimpleTest.dpr The tricky part of comb

Chapter 4: PowerDAQ Software (SDK) 84Method H. Synchronous stimulus/response operation This is subset of Method A. Some applications require a an

Chapter 4: PowerDAQ Software (SDK) 85When starting out, first recognize that a driver for a data acquisition card differs from one for a printer, C

Chapter 4: PowerDAQ Software (SDK) 86 Analog Output Subsystem There are four update modes for the analog output subsystem: • Polled I/O update mo

Chapter 4: PowerDAQ Software (SDK) 87Method B. Buffered event-based waveform mode using PCI interrupts See SDK Examples AOEvents.c, AEOutBlk.vbp