Motorola DSP96002 Instrukcja Użytkownika

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
DSP96002
Order this document by:
DSP96002/D, Rev. 2
©1996 MOTOROLA, INC.
32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT
PROCESSOR
The DSP96002 is designed to support intensive graphic image and numeric processing. It is
a dual-port, low-power, general purpose floating-point processor. The DSP includes 1024
words of data RAM (equally divided into X data and Y data memory), 1024 words of full-
speed on-chip Program RAM, two data ROMs, a dual-channel Direct Memory Access (DMA)
controller, special on-chip bootstrap hardware, and On-Chip Emulation (OnCE™) debug
circuitry. The Central Processing Unit (CPU) consists of three 32-bit execution units
operating in parallel. The DSP96002 has two identical memory expansion ports with control
lines to facilitate interfacing SRAMs, DRAMs (operating in their fast access modes), and
Video RAMs (VRAMs). Each port can be configured as a Host Interface (HI), which
facilitates easy interface with other processors for multiprocessor applications. Linear arrays
of DSP96002s can be implemented without glue logic. The MPU-style programming model
and instruction set allow straightforward generation of efficient, compact code. The high
speed of the DSP96002 makes it well-suited for high bandwidth and numerically intensive
applications that require floating-point processing and access to large memory subsystems.
Figure 1
Block Diagram
Internal
Switch And Bit
Manipulation
Unit
Program Controller
Data
YAB
XAB
PAB
YDB
XDB
PDB
GDB
Program
Decode
Controller
Program
Address
Generator
Program
Interrupt
Controller
Clock
Generator
DDB
Dual Channel
DMA
Controller
Debug
Controller
4
Serial Debug
Port
MODB/IRQB
MODA/IRQA
RESET
External
Address
Switch
Address
Generation
Unit (AGU)
• IEEE Floating Point
• 32 × 32 Integer ALU
CLK
Memory
512 × 32
RAM
Memory
512 × 32
RAM
Program
1024 × 32
RAM and
64 × 32
Bootstrap
ROM
512 × 32†
ROM
512 × 32†
ROM
Data ALU
32-bit Buses
Address
External
Address
Switch
Bus
Control
Control
External
Data
Switch
Port B
Memory
X Data Y Data
32
MODC/IRQC
Bus
Control
Control
Host
Interface
Data
32
*
**
*
*
*
*
Dual Access (DMA/Core)
4
4
1818
Instruction
Cache
TimerTimer
Port A
32
Address
32
1024 × 32 Virtual Locations
32-bit
Host
Interface
32-bit
OnCE
AA0306
Bus
External
Data
Switch
Bus
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
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Podsumowanie treści

Strona 1 - DSP96002

MOTOROLA SEMICONDUCTOR TECHNICAL DATA DSP96002 Order this document by:DSP96002/D, Rev. 2©1996 MOTOROLA, INC. 32-BIT GENERAL PURPOSE FLOATING-POINT

Strona 2 - Data Sheet Conventions

Signal/Connection DescriptionsPort A and Port B 1-6 DSP96002/D, Rev. 2 MOTOROLA PORT A AND PORT B Port A and Port B are identical in pinout and func

Strona 3 - FEATURES

X and Y Memory ROM Tables B-6 DSP96002/D, Rev. 2 MOTOROLA xr:$000006c8= $beac7cd4 $bea986c4 $bea68f12 $bea395c5xr:$000006cc= $bea09ae5 $be9d9e78 $be

Strona 4 - PRODUCT DOCUMENTATION

X and Y Memory ROM Tables MOTOROLA DSP96002/D, Rev. 2 B-7 xr:$0000075c= $3f08f59b $3f0a48ad $3f0b9a6b $3f0cead0xr:$00000760= $3f0e39da $3f0f8784 $3f

Strona 5 - SECTION 1

X and Y Memory ROM Tables B-8 DSP96002/D, Rev. 2 MOTOROLA xr:$000007f0= $3f7ec46d $3f7eea9d $3f7f0e58 $3f7f2f9dxr:$000007f4= $3f7f4e6d $3f7f6ac7 $3f

Strona 6

X and Y Memory ROM Tables MOTOROLA DSP96002/D, Rev. 2 B-9 yr:$00000478= $3f2beb4a $3f2d1469 $3f2e3bde $3f2f61a5yr:$0000047c= $3f3085bb $3f31a81d $3f

Strona 7

X and Y Memory ROM Tables B-10 DSP96002/D, Rev. 2 MOTOROLA yr:$0000050c= $3f7f4e6d $3f7f2f9d $3f7f0e58 $3f7eea9dyr:$00000510= $3f7ec46d $3f7e9bc9 $3

Strona 8

X and Y Memory ROM Tables MOTOROLA DSP96002/D, Rev. 2 B-11 yr:$000005a0= $3f0e39da $3f0cead0 $3f0b9a6b $3f0a48adyr:$000005a4= $3f08f59b $3f07a136 $3

Strona 9 - INTERRUPT AND MODE CONTROL

X and Y Memory ROM Tables B-12 DSP96002/D, Rev. 2 MOTOROLA yr:$00000634= $bea09ae5 $bea395c5 $bea68f12 $bea986c4yr:$00000638= $beac7cd4 $beaf713a $b

Strona 10 - Freescale Semiconductor, Inc

X and Y Memory ROM Tables MOTOROLA DSP96002/D, Rev. 2 B-13 yr:$000006c8= $bf710908 $bf718f57 $bf721352 $bf7294f8yr:$000006cc= $bf731447 $bf73913f $b

Strona 11

X and Y Memory ROM Tables B-14 DSP96002/D, Rev. 2 MOTOROLA yr:$0000075c= $bf584853 $bf577026 $bf5695e5 $bf55b993yr:$00000760= $bf54db31 $bf53fac3 $b

Strona 12

X and Y Memory ROM Tables MOTOROLA DSP96002/D, Rev. 2 B-15 yr:$000007f0= $bdc8bd36 $bdbc3ac3 $bdafb680 $bda3308cyr:$000007f4= $bd96a905 $bd8a200a $b

Strona 13

Signal/Connection DescriptionsPort A and Port B MOTOROLA DSP96002/D, Rev. 2 1-7 AD0–AD31BD0–BD31Input/OutputTri-stated Data Bus —D0–D31 are tri-stat

Strona 14

X and Y Memory ROM Tables B-16 DSP96002/D, Rev. 2 MOTOROLA Freescale Semiconductor, I Freescale S

Strona 15

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee re

Strona 16

Signal/Connection DescriptionsPort A and Port B 1-8 DSP96002/D, Rev. 2 MOTOROLA ATTBTTOutput Tri-stated Transfer Type —TT is an output when the DSP

Strona 17

Signal/Connection DescriptionsPort A and Port B MOTOROLA DSP96002/D, Rev. 2 1-9ATABTAInput Input, ignored during resetTransfer Acknowledge— The TA inp

Strona 18

Signal/Connection DescriptionsPort A and Port B 1-10 DSP96002/D, Rev. 2 MOTOROLAADEBDEInput Input, ignored during resetData Enable—DE is an input that

Strona 19 - TIMER/EVENT COUNTER

Signal/Connection DescriptionsPort A and Port B MOTOROLA DSP96002/D, Rev. 2 1-11AHABHAInput Input Host Acknowledge—HA is an input that may change asyn

Strona 20 - OnCE PORT

Signal/Connection DescriptionsPort A and Port B 1-12 DSP96002/D, Rev. 2 MOTOROLAABGBBGInput Input, ignored during resetBus Grant—BG is an input that m

Strona 21

Signal/Connection DescriptionsPort A and Port B MOTOROLA DSP96002/D, Rev. 2 1-13ABABBAOutput Tri-stated Bus Acknowledge—BA is an open drain output. Wh

Strona 22

Signal/Connection DescriptionsPort A and Port B 1-14 DSP96002/D, Rev. 2 MOTOROLAABBBBBInput Input Bus Busy—BB is an input that must be asserted and de

Strona 23 - SPECIFICATIONS

Signal/Connection DescriptionsTimer/Event Counter MOTOROLA DSP96002/D, Rev. 2 1-15TIMER/EVENT COUNTERTable 1-7 Timer/Event Counters Signal NameTypeS

Strona 24 - THERMAL CHARACTERISTICS

ii DSP96002/D, Rev. 2 MOTOROLATABLE OF CONTENTS SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS. . . . . . . . . . . . . . . . . . 1-1SECTION 2 SPECIFICATI

Strona 25 - DC ELECTRICAL CHARACTERISTICS

Signal/Connection DescriptionsOnCE Port 1-16 DSP96002/D, Rev. 2 MOTOROLAOnCE PORTTable 1-8 On-Chip Emulation Port (OnCE) Signals Signal NameSignalT

Strona 26

Signal/Connection DescriptionsOnCE Port MOTOROLA DSP96002/D, Rev. 2 1-17DSO Output Output, pulled highDebug Serial Output—Data contained in one of the

Strona 27 - AC ELECTRICAL CHARACTERISTICS

Signal/Connection DescriptionsOnCE Port 1-18 DSP96002/D, Rev. 2 MOTOROLA Freescale Semiconductor, I

Strona 28 - Clock Operation

MOTOROLA DSP96002/D, Rev. 2 2-1 SECTION 2 SPECIFICATIONS INTRODUCTION The digital signal processor (DSP) is fabricated using high-density Complement

Strona 29 - Arbitration Bus Timing

SpecificationsThermal Characteristics 2-2 DSP96002/D, Rev. 2 MOTOROLA THERMAL CHARACTERISTICS Table 2-1 Maximum Electrical Ratings Rating Symbol

Strona 30

SpecificationsDC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-3 DC ELECTRICAL CHARACTERISTICS Table 2-3 DC Electrical Characteristics

Strona 31

SpecificationsDC Electrical Characteristics 2-4 DSP96002/D, Rev. 2 MOTOROLA Output Low VoltageI OL = 3.2 mAV OL — — 0.4 VPower Dissipationf = 33.3

Strona 32 - External Bus Relative Timing

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-5 AC ELECTRICAL CHARACTERISTICS The timing waveforms shown in this section

Strona 33

SpecificationsAC Electrical Characteristics 2-6 DSP96002/D, Rev. 2 MOTOROLAClock OperationThe DSP96002 system clock is derived from a crystal or an ex

Strona 34

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-7Arbitration Bus TimingTable 2-5 Arbitration Bus Timing No.1Characteristic

Strona 35

DSP96002Features MOTOROLA DSP96002/DRev. 2 iii FEATURES • Digital signal processing core– Efficient 32-bit DSP engine– Conforms to IEEE 754-1985 sta

Strona 36

SpecificationsAC Electrical Characteristics 2-8 DSP96002/D, Rev. 2 MOTOROLAFigure 2-3 Bus Acquisition TimingCLK(input)(Tri-state)(Tri-state)(Tri-state

Strona 37

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-9Figure 2-4 Bus Release TimingCLK(input)(Tri-state)(Tri-state)(Tri-state)BR(

Strona 38

SpecificationsAC Electrical Characteristics 2-10 DSP96002/D, Rev. 2 MOTOROLAExternal Bus Relative TimingTable 2-6 External Bus Relative Timing No.1C

Strona 39

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-1119aWR Deasserted to D0–D31 Three-state (Write Cycle)—1619— 13.519—1119ns20

Strona 40 - Multiplexed Bus Timing

SpecificationsAC Electrical Characteristics 2-12 DSP96002/D, Rev. 2 MOTOROLAFigure 2-5 External Bus Relative Timing(Tri-state)(Tri-state)R/W(output)TS

Strona 41

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-13External Bus Synchronous TimingTable 2-7 External Bus Synchronous Timing

Strona 42 - Host Timing

SpecificationsAC Electrical Characteristics 2-14 DSP96002/D, Rev. 2 MOTOROLA45 BS Asserted to TA Asserted5.—1510— 12.511— 9.511ns46 TA Valid to CLK Hi

Strona 43

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-15Figure 2-6 External Bus Synchronous Timing—No Wait StatesCLK(input)TA(inpu

Strona 44

SpecificationsAC Electrical Characteristics 2-16 DSP96002/D, Rev. 2 MOTOROLAFigure 2-7 External Bus Synchronous Timing—One Wait StateCLK(input)A0–A31,

Strona 45

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-17Figure 2-8 Read-Modify-Write Cycle Timing—No Wait StatesCLK(input)A0–A31,S

Strona 46

DSP96002Product Documentation iv DSP96002/DRev. 2 MOTOROLA – Off-chip expansion to 2 × 2 32 32-bit words of data memory– Off-chip expansion to 2

Strona 47 - OnCE Timing

SpecificationsAC Electrical Characteristics 2-18 DSP96002/D, Rev. 2 MOTOROLAMultiplexed Bus TimingTable 2-8 Multiplexed Bus Timing No.1Characteristi

Strona 48

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-19Figure 2-9 Address Bus Enable/Disable TimingFigure 2-10 Data Bus Enable/Di

Strona 49

SpecificationsAC Electrical Characteristics 2-20 DSP96002/D, Rev. 2 MOTOROLAHost TimingTable 2-9 Host Timing No.1Characteristic233.3 MHz340 MHz460 M

Strona 50

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-21115HS, HA Deasserted to TS Asserted (Setup)1—0—0—ns118 HA Width Asserted (

Strona 51

SpecificationsAC Electrical Characteristics 2-22 DSP96002/D, Rev. 2 MOTOROLAFigure 2-11 Host Read Cycle Timing (Non-DMA Mode)Figure 2-12 Host Write Cy

Strona 52

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-23Figure 2-13 Host Read Cycle Timing (DMA Mode)Figure 2-14 Host Write Cycle

Strona 53

SpecificationsAC Electrical Characteristics 2-24 DSP96002/D, Rev. 2 MOTOROLAFigure 2-16 Host Request Timing123121122120HR(output)CLK(input)TS, HA(inpu

Strona 54

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-25OnCE TimingTable 2-10 OnCE Timing No.1Characteristic233.3 MHz340 MHz460

Strona 55

SpecificationsAC Electrical Characteristics 2-26 DSP96002/D, Rev. 2 MOTOROLANote: 1. The numbers in this column are shown as circled numbers in the fo

Strona 56

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-27Figure 2-19 OnCE Data I/O to Status TimingFigure 2-20 OnCE Status to Data

Strona 57

MOTOROLA DSP96002/D, Rev. 2 1-1 SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS SIGNAL GROUPINGS The input and output signals of the DSP96002 are organized

Strona 58 - Timer/Event Counter

SpecificationsAC Electrical Characteristics 2-28 DSP96002/D, Rev. 2 MOTOROLAReset, Mode Select, Interrupt TimingFigure 2-22 OnCE DSCK Next Command Aft

Strona 59

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-29170Delay from A0–A31, S0–S1, R/W, BS, and TT Valid Caused by First Interru

Strona 60

SpecificationsAC Electrical Characteristics 2-30 DSP96002/D, Rev. 2 MOTOROLAFigure 2-23 Reset Entry TimingFigure 2-24 Asynchronous Reset Exit TimingFi

Strona 61 - PACKAGING

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-31Figure 2-26 Operating Mode Select TimingFigure 2-27 External Edge-Triggere

Strona 62 - TOP VIEW GND

SpecificationsAC Electrical Characteristics 2-32 DSP96002/D, Rev. 2 MOTOROLAWAIT, STOP, DMA Request TimingTable 2-12 WAIT, STOP, DMA Request Timing

Strona 63 - BOTTOM VIEW GND

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-33189CLK Low to DSO (ACK) Valid (Enter Debug Mode)• After Synchronous Recove

Strona 64

SpecificationsAC Electrical Characteristics 2-34 DSP96002/D, Rev. 2 MOTOROLAFigure 2-29 Recovery from WAIT State Using Synchronous Interrupt TimingFig

Strona 65

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-35Figure 2-32 Recovery from STOP State Using Asynchronous Interrupt TimingFi

Strona 66

SpecificationsAC Electrical Characteristics 2-36 DSP96002/D, Rev. 2 MOTOROLATimer/Event CounterFigure 2-35 External DMA Request TimingTable 2-13 Tim

Strona 67

SpecificationsAC Electrical Characteristics MOTOROLA DSP96002/D, Rev. 2 2-37Figure 2-36 TIO Timer Event Input RestrictionsFigure 2-37 External Pulse G

Strona 68

Signal/Connection DescriptionsSignal Groupings 1-2 DSP96002/D, Rev. 2 MOTOROLA Figure 1-1 Functional Group Pin AllocationsAddress Bus AAA0–AA31 Dat

Strona 69

SpecificationsAC Electrical Characteristics 2-38 DSP96002/D, Rev. 2 MOTOROLA Freescale Semiconductor, I

Strona 70

MOTOROLA DSP96002/D, Rev. 2 3-1 SECTION 3 PACKAGING This section contains package and pin-out information for the DSP96002. There are two package o

Strona 71 - Go to: www.freescale.com

PackagingPGA Package 3-2 DSP96002/D, Rev. 2 MOTOROLA PGA PACKAGE Figure 3-1 Top View of the DSP96002 223-pin PGA Package123456789101112131415161718

Strona 72

PackagingPGA Package MOTOROLA DSP96002/D, Rev. 2 3-3 Figure 3-2 Bottom View of the DSP96002 223-pin PGA Package123456789101112131415161718VDSO DSI

Strona 73

PackagingPGA Package 3-4 DSP96002/D, Rev. 2 MOTOROLATable 3-1 DSP96002 Pin List, 223-pin PGA Package Pin NumberSignal Type Signal NameA1 Input/Outpu

Strona 74

PackagingPGA Package MOTOROLA DSP96002/D, Rev. 2 3-5B18 Input/Output AA20C1 Input/Output BA17C2 Input/Output BA21C3 Input/Output BA26C4 Input GNDNC5 I

Strona 75

PackagingPGA Package 3-6 DSP96002/D, Rev. 2 MOTOROLAE1 Input/Output BA13E2 Input/Output BA16E3 Input/Output BA22E4 Input GNDNE15 Input GNDNE16 Input/O

Strona 76

PackagingPGA Package MOTOROLA DSP96002/D, Rev. 2 3-7J15 Input GNDQJ16 Input/Output AD24J17 Input/Output AD25J18 Input/Output AD23K1 Input/Output BA04K

Strona 77

PackagingPGA Package 3-8 DSP96002/D, Rev. 2 MOTOROLAP1 Input/Output BR/WP2 Input/Output BTSP3 Output BBLP4 Input GNDNP15 Input GNDNP16 Input/Output AD

Strona 78

PackagingPGA Package MOTOROLA DSP96002/D, Rev. 2 3-9T11 Input/Output BD14T12 Input/Output BD11T13 Input/Output BD07T14 Input/Output BD04T15 Input/Outp

Strona 79

Signal/Connection DescriptionsPower MOTOROLA DSP96002/D, Rev. 2 1-3 POWERGROUND Table 1-2 Power Inputs Power Name Description V CCN Normal Power

Strona 80

PackagingPGA Package 3-10 DSP96002/D, Rev. 2 MOTOROLAV9 Input/Output BD20V10 Input/Output BD19V11 Input/Output BD16V12 Input/Output BD13V13 Input/Outp

Strona 81

PackagingCQFP Package MOTOROLA DSP96002/D, Rev. 2 3-11CQFP PACKAGEFigure 3-4 Top View of the DSP96002 240-pin CQFP PackageOrientation Mark123456789101

Strona 82

PackagingCQFP Package 3-12 DSP96002/D, Rev. 2 MOTOROLAFigure 3-5 Bottom View of the DSP96002 240-pin CQFP PackageOrientation Mark123456789101112131415

Strona 83 - DESIGN CONSIDERATIONS

PackagingCQFP Package MOTOROLA DSP96002/D, Rev. 2 3-13Table 3-2 DSP96002 Pin List, 240-pin CQFP Package Pin NumberSignal Type Signal Name1 N/A NC2 N

Strona 84

PackagingCQFP Package 3-14 DSP96002/D, Rev. 2 MOTOROLA35 Input/Output AA0436 Input/Output AA0537 Input/Output AA0638 Input/Output AA0739 Input GNDQ40

Strona 85

PackagingCQFP Package MOTOROLA DSP96002/D, Rev. 2 3-1570 Input/Output AA2771 Input GNDN72 Input/Output AA2873 Input/Output AA2974 Input/Output AA3075

Strona 86

PackagingCQFP Package 3-16 DSP96002/D, Rev. 2 MOTOROLA104 Input/Output AD10105 Input/Output AD09106 Input/Output AD08107 Input VCCN108 Input/Output AD

Strona 87 - POWER-UP CONSIDERATIONS

PackagingCQFP Package MOTOROLA DSP96002/D, Rev. 2 3-17140 Input/Output BD13141 Input/Output BD14142 Input/Output BD15143 Input GNDQ144 Input VCCQ145 I

Strona 88

PackagingCQFP Package 3-18 DSP96002/D, Rev. 2 MOTOROLA176 Input GNDN177 Output BBA178 N/A NC179 N/A NC180 N/A NC181 N/A NC182 N/A NC183 N/A NC184 N/A

Strona 89 - ORDERING INFORMATION

PackagingCQFP Package MOTOROLA DSP96002/D, Rev. 2 3-19211 Input GNDQ212 Input CLK213 Input VCCQ214 Output BA08215 Output BA09216 Output BA10217 Output

Strona 90

Signal/Connection DescriptionsClock 1-4 DSP96002/D, Rev. 2 MOTOROLA CLOCK Table 1-4 Clock Signal Signal Name TypeState During ResetSignal Descri

Strona 91 - BOOTSTRAP CODE FOR DSP96002

PackagingCQFP Package 3-20 DSP96002/D, Rev. 2 MOTOROLAFigure 3-6 DSP96002 Mechanical Information, 240-pin CQFP PackageCASE 988-01ISSUE ENOTES:1. ALL D

Strona 92 - Bootstrap Code for DSP96002

PackagingPackage and Pin-Out Information MOTOROLA DSP96002/D, Rev. 2 3-21PACKAGE AND PIN-OUT INFORMATIONComplete mechanical information regarding DSP9

Strona 93

PackagingPackage and Pin-Out Information 3-22 DSP96002/D, Rev. 2 MOTOROLA Freescale Semiconductor, I

Strona 94

MOTOROLA DSP96002/D, Rev. 2 4-1 SECTION 4 DESIGN CONSIDERATIONS THERMAL DESIGN CONSIDERATIONS An estimation of the chip junction temperature, T J ,

Strona 95 - X AND Y MEMORY ROM TABLES

Design ConsiderationsThermal Design Considerations 4-2 DSP96002/D, Rev. 2 MOTOROLA The thermal performance of plastic packages is more dependent on

Strona 96

Design ConsiderationsElectrical Design Considerations MOTOROLA DSP96002/D, Rev. 2 4-3 ELECTRICAL DESIGN CONSIDERATIONS Use the following list of rec

Strona 97

Design ConsiderationsPower Consumption Considerations 4-4 DSP96002/D, Rev. 2 MOTOROLA POWER CONSUMPTION CONSIDERATIONS Power dissipation is a key is

Strona 98

Design ConsiderationsPower-Up Considerations MOTOROLA DSP96002/D, Rev. 2 4-5 POWER-UP CONSIDERATIONS To power-up the device properly, ensure that th

Strona 99

Design ConsiderationsPower-Up Considerations 4-6 DSP96002/D, Rev. 2 MOTOROLA Freescale Semiconductor, I

Strona 100

MOTOROLA DSP96002/D, Rev. 2 5-1 SECTION 5 ORDERING INFORMATION Consult a Motorola Semiconductor sales office or authorized distributor to determine

Strona 101

Signal/Connection DescriptionsInterrupt and Mode Control MOTOROLA DSP96002/D, Rev. 2 1-5 INTERRUPT AND MODE CONTROL Table 1-5 Interrupt and Mode

Strona 102

Ordering Information 5-2 DSP96002/D, Rev. 2 MOTOROLA Freescale Semiconductor, I Freescale Semicon

Strona 103

MOTOROLA DSP96002/D, Rev. 2 A-1 APPENDIX A BOOTSTRAP CODE FOR DSP96002 ; BOOTSTRAP CODE FOR DSP96002 -  Copyright 1988 Motorola Inc. ; ; Host a

Strona 104

Bootstrap Code for DSP96002 A-2 DSP96002/D, Rev. 2 MOTOROLA ; The second routine loads the internal PRAM using the Host ; Interface logic. ; If HF

Strona 105

Bootstrap Code for DSP96002 MOTOROLA DSP96002/D, Rev. 2 A-3 ; Host load routine_HOSTR_LBL11 JCLR #3,X:(R2),_LBL22; if HF0=1, stop loadi

Strona 106

Bootstrap Code for DSP96002 A-4 DSP96002/D, Rev. 2 MOTOROLA Freescale Semiconductor, I Freescale

Strona 107

MOTOROLA DSP96002/D, Rev. 2 B-1 APPENDIX B X AND Y MEMORY ROM TABLES Table B-1 X Memory ROM Contents (full cycle of cosine values) xr:$00000400

Strona 108

X and Y Memory ROM Tables B-2 DSP96002/D, Rev. 2 MOTOROLA xr:$00000478= $3f3daef9 $3f3ca003 $3f3b8f3b $3f3a7ca4xr:$0000047c= $3f396842 $3f385216 $3f

Strona 109

X and Y Memory ROM Tables MOTOROLA DSP96002/D, Rev. 2 B-3 xr:$0000050c= $bd96a905 $bda3308c $bdafb680 $bdbc3ac3xr:$00000510= $bdc8bd36 $bdd53db9 $bd

Strona 110

X and Y Memory ROM Tables B-4 DSP96002/D, Rev. 2 MOTOROLA xr:$000005a0= $bf54db31 $bf55b993 $bf5695e5 $bf577026xr:$000005a4= $bf584853 $bf591e6a $bf

Strona 111

X and Y Memory ROM Tables MOTOROLA DSP96002/D, Rev. 2 B-5 xr:$00000634= $bf731447 $bf7294f8 $bf721352 $bf718f57xr:$00000638= $bf710908 $bf708066 $bf

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